Hello All,
We are kicking Altium to the curb after much abuse at the hands of their software developers over the years.
I'm trying to translate the Altium ASCII PcbDoc file and the process repeatedly terminates in the Command Window: as shown below without actually producing the translated .brd file.
Performing a partial design check before saving.
Writing design to disk.
'unnamed.brd' saved to disk.
Performing a partial design check before saving.
Writing design to disk.
'03_CentralGateway_Logic.brd' saved to disk.
*Error* quotient: Attempted to divide by zero
The final lines of the Altium translator process is shown below.
4.3.1 INFO - [575] Start Component "TP1214" with Footprint "TP200" SCH_FOOTPRINT: nil - ("TP200" "TP200_3" "3" 1 "TP1214" 42007.52 20643.94 "BOTTOM" nil 90.0 "TP1214" "TP200")
-------------------------------------------------------------------------------
4.3.2 INFO - For Component "TP1214" Footprint "TP200" already exist.
4.3.11 INFO - Footprint "TP200" ID: dbid:000001C9249BF6B0 t created
-------------------------------------------------------------------------------
===============================================================================
4.3.0 INFO - END of [ 575] Successful footprints creation of [ 575] Total - End Time: ["Oct 25 08:55:46 2022"]
===============================================================================
===============================================================================
X.1.02 INFO - Board File: "./translator.run/02_CentralGateway_Dump.brd" saved | DBCheck: Errors = 44; Warnings = 1
===============================================================================
4.0.0 INFO - Start to Create Device File.. - Start Time: ["Oct 25 08:55:47 2022"]
===============================================================================
4.0.1 INFO - Footprint Mode set to Generic.
-------------------------------------------------------------------------------
===============================================================================
4.0.0 INFO - End of [ 1] Successful Device File Creation of [ 1] Total - End Time: ["Oct 25 08:55:47 2022"]
===============================================================================
===============================================================================
4.7.0 INFO - Start to Create [575] Component AND Net Logic - Start Time: "Oct 25 08:55:47 2022"
===============================================================================
4.7.1 INFO - Footprint Mode set to Generic.
-------------------------------------------------------------------------------
4.7.2 INFO - Part and net logic sourced from schematic.
===============================================================================
4.7.0 INFO - END of [ 1] Successful Component and Net Logic Creation of [ 1] Total - END Time: ["Oct 25 08:55:47 2022"]
===============================================================================
===============================================================================
X.1.03 INFO - Board File: "./translator.run/03_CentralGateway_Logic.brd" saved | DBCheck: Errors = 0; Warnings = 1
-------------------------------------------------------------------------------
3.0.0 INFO - Start for Board Setup...
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
3.0.1 INFO - Start to clear all existing data first
-------------------------------------------------------------------------------
3.2.0 INFO - Start to add Board Records
===============================================================================
Please help me out with some suggestions to get me past this if you can.
Thank you,
MrStrange