What are Constraints?
A constraint is a user-defined requirement applied to a net or another interconnect object in a design. Constraints are used to the audit routed interconnect, determining whether the interconnect complies with or violates the requirement. Constraints also drive many interactive and automatic routing behaviors.
Type of Constraints:
The different types of constraints in the Constraint Manager are Electrical, Physical, Spacing, Same Net Spacing, Assembly and Manufacturing.
This post will focus on electrical constraints and what all electrical constraints can be set up when working on a design:
Electrical constraints are constraints that are determined from electrical performance requirements. Electrical constraints contain rules controlling the electrical behavior of a net, bus, or differential pair.
Electrical constraints apply to all parts of a net, regardless of the ETCH/CONDUCTOR subclass or layout area. Therefore, constraint areas do not apply to electrical constraints, and there is no assignment table for them. Instead, when you assign an electrical constraint set to a net, the ELECTRICAL_CONSTRAINT_SET property attaches to the net that is set to the name of that constraint set.
In Allegro PCB Designer and Allegro Package Designer Plus, the constraints are set up in Constraint Manager.
You set rules in the Electrical Constraint Set section and apply the rules to the nets in the Nets section.
The Electrical Constraint worksheet in Constraint Manager consists of the following electrical constraints that are explained briefly here:
1. Signal Integrity
a) Electrical Properties: This is a collection of six subitems.
Frequency/Period: This specifies the frequency of the net in MHz. You can also specify the frequency as a period in nanoseconds.
Duty Cycle: This specifies the duty cycle of the net.
Jitter: This specifies the amount of clock jitter in picoseconds when switching between high and low states (this is expressed in absolute time).
Cycle to Measure: This specifies the numerical cycle to measure data during simulations.
Offset: This specifies the clock/strobe offset in nanoseconds for bus simulations.
Bit Pattern: This specifies the stimulus bit pattern to use for a bus simulation.
b) Reflection: Following constraints can be captured to define the requirements for a comprehensive simulation:
Overshoot Max: This specifies the absolute high: low value in millivolts, which is allowed for any pin on the net. The low value for ‘max overshoot low’ is sometimes also referred to as the minimum undershoot.
Noise Margin Min: This specifies the absolute delta in millivolts between the undershoot at receiver and its relevant logic high or low threshold.
c) Edge Distortions: Following constraints can be captured to define the requirements for a comprehensive simulation:
Edge Sensitivity: This specifies whether the receivers are sensitive to non-monotonicity.
First Incident Switch: This specifies whether the receivers of all driver/receiver pin pairs are required to switch on the first incident wave.
Estimated and Simulated Xtalk: Following constraints can be captured to define the requirements for estimated and simulated Xtalk.
Active Window: This specifies the window when a net is switching and creating noise.
Sensitive Window: This specifies the window when a net is steady and susceptible to noise.
Nets: This specifies the list of nets to ignore when calculating crosstalk.
Max Xtalk: This specifies the maximum allowable crosstalk on the victim held at steady state high: low from all aggressor nets.
Max Peak Xtalk: This specifies the maximum allowable crosstalk on the victim held at steady state high: low from a single aggressor net.
d) SSN: SSN is the potential noise induced on a driver pin if all pins on a component, which use the same power/ground nets, switch states simultaneously.
Max SSN: This specifies the maximum noise. This may be defined as two values that represent the budget for both high: low states.
Power Bus Name: This specifies the name of the power bus associated with the driver pin of the XNet/Net.
Ground Bus Name: This specifies the name of the ground bus associated with the driver pin of the XNet/Net.
2. Timing: Timing constraints and properties use the characteristics of a clock or strobe net and compare this with the delay of the object itself to ensure that the Setup and Hold requirements are met, and specify the allowable delays in a driver: receiver path.
a) Switch/Settle Delays
Min First Switch :- Specifies the minimum allowable delay in nanoseconds for a driver: receiver path to first cross its switching threshold. This is defined with two values which represent the budget for both the rising: falling edges.
Max Final Settle: This specifies the maximum allowable delay in nanoseconds for a driver: receiver path to reach its final high or low state. This is defined with two values that represent the budget for both rising: falling edges.
b) Setup/Hold (Common Clock)
Clock: This specifies the name of the clocking net.
Clock 2Out: This specifies the minimum/maximum delay in nanoseconds from the active clock trigger to the output change in the launching component.
Clock Skew: This specifies the minimum/maximum skew in the clock signal between the launching and latching components.
Interconnect Delay :- You can simulate the interconnect delay between the launching and latching component using the actual First Switch and Final Settle delays, or you can explicitly define it to experiment with different delays.
c) Setupand Hold
MIN_SETUP: This specifies the minimum time in nanoseconds that a data signal must be in a steady state relative to the clocking characteristics.
MIN_HOLD: This specifies the minimum hold time in nanoseconds that a data signal must be in a steady state relative to the clocking characteristics.
3. Routing
Wiring: Wiring constraints define topology scheduling parameters, physical (Stub Length), electromagnetic interference (EMI) (Max Exposed Length) rules, Max Parallel rules and Layer Set rules.
Vias: For Via constraints, you can define the maximum vias on a net, match via count, and set Via structure for the net
Impedance: In this worksheet, you can check for single-line impedance. You specify both Target and Tolerance impedance requirement for the etch. The target impedance is as an absolute value in Ohms, whereas the tolerance can be an absolute value in Ohms or as a percentage.
Min/Max Propagation Delays: Propagation delay constraint is used to specify the minimum and maximum delay requirements for a pin pair.
Total Etch length: Total Etch constraint is used to specify the minimum and maximum etch requirements for an XNet or net.
Differential Pair: In this worksheet, the electrical-related differential pair constraints are added, like the Uncoupled length, and Static and Dynamic Phase tolerances. The differential pair primary/neck gap and primary/neck width values can be set both in Electrical worksheet and Physical worksheet.
Relative Propagation Delay: Relative Propagation Delay constraint is used to specify the matching or relative delay requirements for a group of pin pairs. Matching implies that the pin pairs have the same delay within a specified tolerance. To be relative implies that the Pin Pairs have a delay which has some relation to a target in the group.
Return Path: This is a net-based constraint that identifies segments of a netlist with potential current return path problems, where the path of the return current deviates from that of the signal. The constraint is assigned to nets and net hierarchies, such as buses, net groups, and differential pairs. To specify return path DRC, set Reference Nets, Reference Layers, and optionally, Ignore Layers. Set Length Ignore on objects to ignore individual reference loss less than a specified value. Use Actual and Margin to cross-probe DRCs in PCB Editor. Also, set the Allowed Pad Gap Distance rule to flag the loss of reference plane for nets joining pads. Set a Stitch Via Distance value to verify that a return path via is within a radius dimension of a via transition. The Adjacent Void Spacing constraint of the return path is considered when a cline is closer to a void than the value specified for the Adjacent Void Spacing constraint.
Stay tuned to this space for more information on Electrical Constraints!!
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