Stacked Vias and the Importance of Limiting to Two Laminations for Reliable PCB Production

Stacked Vias and the Importance of Limiting to Two Laminations for Reliable PCB Production

In high-density PCB designs, stacked vias have become increasingly popular to enable complex interconnects within tight spaces. While stacked vias can be a powerful tool in miniaturizing electronics, they also introduce significant reliability risks—especially when more than two lamination cycles are involved.

Why Limit Stacked Vias to Two Laminations?

Each lamination cycle in PCB manufacturing involves heating and pressing layers together. When vias are stacked across multiple laminations (3 or more), the risks increase substantially:

• Misalignment tolerance narrows: Each additional lamination increases the risk of layer shift, which can lead to via misalignment and open circuits.
• Resin shrinkage stress: Repeated heating cycles stress the resin system and copper plating, increasing the likelihood of cracks in the via barrels—especially in the innermost stacked vias.
• Copper fatigue and reliability drops: Electroplated copper in stacked vias is more prone to cracking due to CTE (Coefficient of Thermal Expansion) mismatch stress if not properly reinforced with plating or filled correctly.

Best practice in the industry is to limit stacking to two laminations (i.e., one sequential lamination step after the core), which dramatically improves structural reliability and manufacturability.

Selecting the Right Factory for Stacked Vias

Stacked via reliability is highly dependent on factory capabilities. The following factors are essential when selecting a supplier:

1. Sequential lamination experience: Ensure the factory has proven experience with high-layer-count boards and stacked via structures. Ask for IPC-6012 Class 3 reports and FAI documentation from similar builds.
2. Via fill and plating technology: Look for laser-drilled microvia fill with vacuum-assisted copper plating or conductive fill materials like epoxy-copper paste. Poor via fill can lead to voids or poor thermal conduction.
3. X-ray inspection and micro-sectioning: The factory must offer 100% stacked via x-ray inspection and cross-sectional analysis as part of their release process.
4. Process control and documentation: A capable factory provides full traceability and statistical process control (SPC) data to track plating thickness and lamination pressure/temp across batches.

A factory’s certifications (EN9120, IATF16949, IPC-A-600 Class 3 compliance) are not just checkboxes—they reflect discipline in manufacturing practices crucial for stacked via reliability.

Who Should Manage Sourcing? Comparison between OEM vs. EMS vs. Broker

Key Risks to Consider

• Delamination due to over-lamination cycles
• Via collapse or misalignment in stacked builds
• Field failures from underplated or poorly filled vias
• Lack of proper thermal/vibration testing in cost-driven factories

Conclusion

Stacked vias are a powerful design feature—but only when implemented with tight process control and the right supplier. Limiting the build to a maximum of two laminations enhances reliability and reduces mechanical stress on the interconnects. OEMs must carefully consider who manages the PCB sourcing—whether it's themselves, their EMS provider, or a specialized broker. For mission-critical or high-speed applications, the choice of partner and factory is just as important as the design itself.

Have you run into reliability issues with stacked vias or multiple lamination cycles in your projects?
What design or manufacturing lessons have you learned when dealing with stacked vias in HDI PCBs?
I'd love to hear about your experiences, challenges, or any alternative approaches you’ve taken.

Let’s open this up for discussion—drop your thoughts, questions, or even a photo of a tricky via stack-up you've tackled!