Hello,
I'm new to SKILL
is there a function to extract the info in the blue circles (pin/via locations and cline segment length and layer) in SKILL?
Thanks
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How to Extract segment length info from Constraint Information
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Get the height value of the textblock from a brd
Hello , I'm a new learner about the pcb skill , there have a issue need your help , thanks in advance!
I want to get the actual height value of the textblock, but now it occur the error when run in brd file.
1.The code is as the following:
(
defun getheight ()
(prog ()
axlSetFindFilter(?enabled '(noall text) ?onButtons '(noall text))
selBox = axlEnterBox()
axlSingleSelectBox(selBox)
allboxes = axlGetSelSet()
foreach(txt allboxes
return(txt->textBlock->height)
))
)
2.The error in the allegro is as following:
E- *Error* get/getq: first arg must be either symbol, list, defstruct or user type - "3"
The picture below is the instructions about the textblock attributes from skill manual.
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how to get the net name of wire using skill script in concept hdl
Hi all, I'm developping a skill scipt in concept hdl. I searched the whole manual but I can not find a way to get a net name of wire. Does anybody have a answer? Thanks a lot
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About the text BBOX
Hi all , I have a problem about the text BBOX in skill.
The BBOX get from a text is just a rectangle area , this area actually is more bigger than the text size, and text also not fullly filled the BBOX area.
So if we just use the BBOX to judge if the text overlap with other text or pin/via , it won't be so accurate. If you have some better methods? Thanks a lot!
(The following green area is the BBOX for text"U123")
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Staggered via
Hi Guys,
i am trying to maintenance the stagger via spacing (0.00mm) after i delete part of it.
any idea how can i do that without place the via all over again.
Eugene
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Making a text string option in a list span 2 lines within Cadence
Looking for a little support on text strings.
I have a form already made conataining some 'default' notes to import onto drawings. The idea being, you choose which note you require, click on the note and it will be added to your design. This structure works fine as it is. However, one of these text string options is rather long, and I would like it to span 2 lines when imported into Cadence as a result of selecting it in this form.
Here is the line of SKILL:
POPUP,t_misc_line:XXXXX-X WITHOUT MARKING,THIS PCB IS TO BE MANUFACTURED IN ACCORDANCE WITH \015 SPECIFICATION XXXXXX - GENERAL REQUIREMENTS SPECIFICATION,ALL 0.XXMM HOLES TO BE RESIN FILLED AND FLAT PLATED OVER
After the colon, the three options are separated using a comma, forming the list of options that become available in the top window of the form created. The middle option (underlined) is the one I want to span 2 lines when brought through into Cadence.
I have read that using ‘\015’ (in red) is an escape sequence for carriage return, however when using this where it is now, it simply gets brought through and included as part of the text string, rather than splitting said text string over 2 lines.
Please can you offer any guidance on if this is possible and how to accomplish it?
Thanks in advance,
Lewis.
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use axlDBChangeText
Hi, I would like to change a text with "axlDBChangeText" but being a novice I must miss something in my code.
Example:
let((b, textBlocks, text)
axlClearSelSet()
axlVisibleDesign(nil)
axlVisibleLayer("REF DES/ASSEMBLY_TOP" t)
axlSelectByName("SYMTYPE" "1206", "REF DES/ASSEMBLY_TOP") ; search and select a refdes 1206
axlAddSelectAll()
b = axlGetSelSet() ; for a o_dbid
axlDBChangeText( car(b) 'refdes nil 1); *WARNING* (axlDBChangeText): Require a text dbid, dbid:00000208B4AD8240
could someone help me out ?
sorry for my english thank you
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Create external DRC for different plating spacing
Hi Guys,
Any idea how to create external DRC to cater the spacing between two type of plating.
Component 1: ENIG plating,(Package geometry/Gold_top are use for this defination)
Component 2: OSP plating,( define by overlap area between soldermask and metal layer in padstack)
Eugene
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Finding duplicates and Renaming Duplicates.
Hai,
I have to find the duplicates element in excel sheet and i need to rename by using skill code can any one please guide me.
For example:
infile like:
sym netname
1 aaa
2 bbb
3 aaa
4 bbb
5 ccc
outfile like: renamed the duplicates
sym netname
1 aaa
2 bbb
3 aaa_1
4 bbb_2
5 ccc
As like this anyone guide me please iam new to skill.
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Wanted to learn Skill coding
Hi Experts,
I wanted to learn about skill coding. I do know nothing about it. Some one please let me know where i can get some documents or demo videos or online course. Please let me know how can i learn. Please help me to learn skill coding.
Thank you,
Leelaprasad
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Regarding making layout from netlist
I have designed a schematic in allegro_design_entry_HDL.
I want to make its layout. But not able to do it, as i am not able to find the option for generating netlist . As per tutuorials it is said to have option of netlist at of Tools > Options > Creste nestlist , but i am not able to get it. And in allegro PCB designer i am not getting any options foe importing netlist. So what should i do .I am not able to proceed Its urgent. I am using allegro 17.2 linux version ? Is ithere any alternative of making layout irrespective of netlist?
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Ask for help about the check pad/via overlap with the text
Hi all , now I have wrote a code to check if the pad/via overlap with the text ,but it always return"Total of text on TOP pad:0"
Could you help to check and give some advice, thanks in advance!
Code shown as following:
<<
(defun refdes_on_pad ()
text_pad = t
layer = "TOP"
turn_on_layer(layer)
unselect_object()
axlSetFindFilter(?enabled '(noall pins vias) ?onButtons '(noall pins vias))
allpads = axlGetSelSet(axlAddSelectAll())
if(text_pad then
cnt = 0
foreach(pads allpads overlap())
axlMsgPut("Total of text on %s pad : %d" layer cnt)
)
)
(defun getpadarea ()
(prog ()
l0 = car(nth(0 pads->bBox))
t0 = cadr(nth(1 pads->bBox))
r0 = car(nth(1 pads->bBox))
b0 = cadr(nth(0 pads->bBox))
x0 = (r0+l0)/2
y0 = (t0+b0)/2
padsold=axlDBGetPad(pads , "PIN/SOLDERMASK_TOP" , "REGULAR")->bBox
padetch=axlDBGetPad(pads , "ETCH/TOP" , "REGULAR")->bBox
ls = car(nth(0 padsold))
ts = cadr(nth(1 padsold))
rs = car(nth(1 padsold))
bs = cadr(nth(0 padsold))
le = car(nth(0 padetch))
te = cadr(nth(1 padetch))
re = car(nth(1 padetch))
be = cadr(nth(0 padetch))
xs = (rs-ls)/2
ys = (ts-bs)/2
xe = (re-le)/2
ye = (te-be)/2
if(xe>xs then
xfinal=xe
yfinal=ye
else
xfinal=xs
yfinal=ys)
l2 = x0-xfinal
t2 = y0+yfinal
r2 = x0+xfinal
b2 = y0-yfinal)
return(list(l2:t2 r2:b2)))
(defun overlap ()
(prog ()
axlSetFindFilter(?enabled '(noall text) ?onButtons '(noall text))
if(axlSingleSelectBox(getpadarea())!= nil then
allbox = axlGetSelSet()
foreach(item allbox
if(item->objType == "text" then
if(item->layer ==strcat("REF DES/SILKSCREEN_" layer)|| item->layer == strcat( "PACKAGE GEOMETRY/SILKSCREEN_" layer) then
axlHighlightObject(list(item))
)
else nil
)
)
)
))
(defun unselect_object ()
(let (allsel)
axlSetFindFilter(?enabled '(noall shapes pins vias text) ?onButtons '(noall shapes pins vias text))
; axlSetFindFilter(?enabled '(all) ?onButtons '(all))
allsel = axlGetSelSet(axlAddSelectAll())
axlClearSelSet()
axlSetFindFilter(?enabled '(noall symbols) ?onButtons '(noall symbols))
allsel = axlGetSelSet(axlAddSelectAll())
axlClearSelSet()
))
(defun turn_on_layer ( layer)
axlVisibleDesign(nil)
Going_On=axlGetParam("paramLayerGroup:BOARD GEOMETRY/paramLayer:OUTLINE")
Going_On->visible=t
axlSetParam(Going_On)
Going_On=axlGetParam(sprintf(dummy "paramLayerGroup:VIA CLASS/paramLayer:%s" layer))
if(layer == "BOTTOM" then
Going_On->visible=t
else
Going_On->visible=nil
)
axlSetParam(Going_On)
Going_On=axlGetParam(sprintf(dummy "paramLayerGroup:PIN/paramLayer:%s" layer))
Going_On->visible=t
axlSetParam(Going_On)
Going_On=axlGetParam(sprintf(dummy "paramLayerGroup:PACKAGE GEOMETRY/paramLayer:SILKSCREEN_%s" layer))
Going_On->visible=t
axlSetParam(Going_On)
Going_On=axlGetParam(sprintf(dummy "paramLayerGroup:REF DES/paramLayer:SILKSCREEN_%s" layer))
Going_On->visible=t
axlSetParam(Going_On)
Going_On=axlGetParam(sprintf(dummy "paramLayerGroup:PACKAGE GEOMETRY/paramLayer:PLACE_BOUND_%s" layer))
Going_On->visible =t
axlSetParam(Going_On)
axlUIWRedraw(nil)
axlClearSelSet()
)
>>
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Toggle ratsnest display via SKILL
Hi all
I have a short SKILL question: I want to toggle the ratsnest display between jogged and straight using SKILL. I use axlDBDisplayControl('ratsnestJog, nil) to set it to straight but using axlDBDisplayControl('ratsnestJog, t) to set it back to jogged doesn't work (axlDBDisplayControl('ratsnestJog t) doesn't work either). Am I doing something wrong?
Thanks,
Martin Ostermayer
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library path issue
Hello Everyone,
I am new cadence pcb designing environment. I am try to create a pcb in cadnce from very scracht.
I started with Design Entry HDL and created a few components schematic and want to transfer it to .brd file.
but when I try to export physical, I received the following message.Could anyone help me in this regards.
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Becoming a PCB designer
I'm already an EE, I really like laying out PCBs I can spend days doing it, measuring components, reading datasheets, however after looking for jobs for a while to do this and i haven't found a single one, to do layout only
PCB Design seems to be a full specialization, however companies expect you to do the programming, product design, industrial design, design pcb, high and low level programming... which i am capable but... I would like to just do PCB layout is there such a job about this?
would getting certified on IPC-A-610, IPC-J-STD-001, IPC-7711\IPC-7721 help me get me a job designing PCBs?
Any suggestions of a program, masters, course i can do to just to live by doing this?
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Becoming a PCB designer
I'm already an EE, I really like laying out PCBs I can spend days doing it, measuring components, reading datasheets, however after looking for jobs for a while to do this and i haven't found a single one, to do layout only
PCB Design seems to be a full specialization, however companies expect you to do the programming, product design, industrial design, design pcb, high and low level programming... which i am capable but... I would like to just do PCB layout is there such a job about this?
would getting certified on IPC-A-610, IPC-J-STD-001, IPC-7711\IPC-7721 help me get me a job designing PCBs?
Any suggestions of a program, masters, course i can do to just to live by doing this?
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axlDBAddProp(dbid list("PINS_ALLOWED")) is adding "VIAS_ALLOWED"
Hi All,
I'm working on a program that adds route keepouts and I am seeing a strange behavior.
The program creates a route keepout then adds the "PINS_ALLOWED" property to the shape.
The user can choose to do the active window or board extents.
When you choose board extents, I get "VIAS_ALLOWED". When I choose active window, I get the correct "PINS_ALLOWED".
The program does not have "VIAS_ALLOWED" anywhere.
I've actually used axlMsgPut and printed out the texted for the property, it prints "PINS_ALLOWED".
The board is uprev'd from 16.6, when "PINS_ALLOWED" did not exist. This is the only thing I can think may cause this.
Any ideas what might cause this?
Thanks,
Jerry
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Looking for ADVFC32 SPICE Model
I'm working on a circuit that requires the input voltage to be converted to a frequency, transmitted over an optical cable, and then converted back to a voltage. I am attempting to simulate this circuit using Eagle ngSpice simulations. The voltage to frequency converters that I am using are ADVFC32 and made by Analog Devices. However, I can't seem to find a SPICE model for this component. Analog Devices does not provide it on their website. Can anyone find a SPICE Model for this part? I'm new to working with electronics so any help/advice you can provide would be appreciated.
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brd2odb with the substitute padflash option to remove top and bottom pads from odb++ output??
Hi all,
We are trying to remove the pads on external layers during brd2odb.
I tried the -p option, but doesn't seem to change anything.
I added a thermal model file an added the -tf and -tm options, now brd2odb starts then stops right away.
Here is a snippet of the code:
OdbInstallDir = axlGetVariable("ALLEGRO_BRD2ODB")
LayoutSite = axlGetVariable("allegro_site")
odbcfgFile = strcat(LayoutSite "/j_share/odb++.config")
full_path = axlGetDrawingName()
odb_jobname = strcat(axlCurrentDesign() "_odb++" )
board_path = getWorkingDir()
sprintf(thermMod "%s%s" getWorkingDir() "./MISTAKE.txt")
modname = "MISTAKE"
sprintf(cmd "\"%s/brd2odb.exe\" -sp -bb -sf -a2l -c p -d -cfg %s -gz -ijp %s -jn %s -jp %s -p s -tf %s -tm %s -o 500 -read_sqa no -skip_refdes no -tr_sym yes " OdbInstallDir odbcfgFile full_path odb_jobname board_path thermMod modname)
axlRunBatchDBProgram("brd2odb" cmd ?noUnload t ?noProgress nil ?noLogview t ?noExitMsgs t)
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PCB Design: Python Scripts: PCB Skill
Hi Everyone,
I am new to skill scripting and trying to understand how the PCB skill is working.
I have a following question.
- Where i can look for basic skill script starting point.
- Where i can check for any APIs?
- How do i find out which register or command or API for what purpose?
- Is there a way python and pcb design can work together?
I mean ; to write some script in python(Which i know) for some PCB design activity and that will run in the PCB design command terminal?
Any leads to starting point?
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