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Allegro - Tip of the Week: Adding Vias - “Working Layer” model"
The Working Layer (WL) model is the recommended method to add conventional or HDI vias.1. Go into the Add Connect command, and then select WL in the Options panel. 2. A pop-up list appears. Enable the...
View ArticleCross-probing issue in OrCAD 22.1
Hi All.Cross probing is not working from board file to schematics. but its working properly in schematics to board file. I'm using OrCAD 22.1-2022-S004Can somebody guide me to fix this...
View ArticleHow to force PCB Designer to update existing design padstacks with newly...
Title says it all really.I need to go back and add tolerances to various drills in the drill table per the board house's request. It's easy enough to go into the padstack file and add those tolerances,...
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PDF is not generated in 16.6 but it is generated in 17.2 ?
Hi Team,i could not generate PDF in 16.6 but if open the same board file in 17.2 . I can generate PDF. Let me explain any one.. why it is happen.. I am using Cadence 16.6 and 17.2 in one system. is i...
View ArticlePCB Editor Sitting on Multiple Licenses
I have been using Cadence for sometime, after a recent addition to the team, we have been experiencing some licensing issues. Basically, it appears that a user can somehow checkout multiple licenses...
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Differential Pair Phase Tolerance DRC
I tried to change a lot of things, but the DRC remains the same. I tried Phase Tuning and Delay Tuning.
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Orcad 22.1 Script to Change grid not working
Hi All,I have been using this script to toggle grid in 17.4 when I try to use the same script in 22.1 I get the output on the command line This is the commandfunckey g 'settoggle gridvalue 0.1 0.25 0.5...
View ArticleDrill hole size vs finished hole size chart
On my drill chart, they all call out for the "finished size" for all holes (through hole, blind vias, and microvias). The fabrication house that I talked to requested to have the drill size shown...
View ArticleConstrain Manager: LayerSubTypes.xml could not be read
I'm having some issues with constrain manager and I'm trying to figure out why I'm getting this error.OS = RHEL7.9SPB174Constrain ManagerCDS_SITE-specific configuration file LayerSubTypes.xml could not...
View ArticleComponent placement and its importance
Placing components on the board is one of the major steps in the complete cycle of board production, starting from schematic design until the physical board goes into the product or system. Component...
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How to create own user -defined Menu in cadence allegro (PCB Editor) ?
Hi Everyone,I need to add own user defined Menu in PCB Editor in 17.X version. i need to add Placement and Routing Menu after Tools Menu. can you any help , How to map ?Under Placement i need add...
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Creating a cavity on top layer
I am in the midst of designing a PCB and I am having trouble figuring out how to create a rectangular cavity on the top layer. In the rectangular cavity (second layer) I also have to create a circular...
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Removing VG DRC
Hi all,Is there any fabrication difficulties or reliability issues when ignoring the VG DRC?image attached for referenceRegards,Jithindev
View ArticleCan a group of nets be forced onto specific layers with CM?
I'm trying to see if I can use Constraint Manager in V17.2, to create a DRC if a group of nets are not kept on the same layer. For some FPGA bank routing the designer wants to ensure that routes within...
View ArticlePrevent Allegro from declaring the path of the project file in the .art...
By default, the second line of a “.art” file shows the full path of the source “.brd” project file. Here is a typical example:G04 Layout Name: M:/……./myProject.brd*Is there some environment variable...
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How to print report to pdf
Hi Everybody,I am working on a script that generates documentation. I would like to attach a file containing board information and a pick and place file to the assembly drawings. I would like to use a...
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Global Saving of Added Subclasses to Visibility Pane?
Allegro v17.4Is there a way to save the subclasses added to the visibility pane such that they show-up on all board files?Right now, they only show-up on the specific board that I added them to.I added...
View ArticleWhat is the size/ block range for Ref-Des text on Silk screen?
Hi,I am new at working with Cadence Allegro, learning new features every time I use it.For silk screen text / Ref Des is there any font size range.? Please help with the list if so..Also, how can we...
View ArticleCheckbox in the FORM in the OrCAD PCB Designer
Hi Everybody,I have a FORM with two Checkboxes e.g. "X" and "Y".How to check which of the keys has been selected?Example:case( FORM -> curField ("X" "Y"...
View ArticleDifferent ways to output your board design and associated challenges
Once your printed circuit board is designed, the next step is to manufacture the board for assembly. For this, the designer needs to create a set of files to send to the fabrication house. There are...
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